1. Technical Field
The present invention relates to semiconductor processing, and more particularly to complementary metal oxide semiconductor devices having different materials for n-type and p-type fin devices on a same chip.
2. Description of the Related Art
Fin field effect transistors (finFETs) have become a mainstream complementary metal oxide semiconductor (CMOS) technology since 22 nm nodes have been implemented. To further improve finFET CMOS performance, Si n-type FETs (NFETs) and SiGe p-type FETs (PFETs) have been pursued for smaller nodes sizes.
A conventional approach for Si NFETs and SiGe PFETs includes recessing Si in a PFET region, epitaxially growing a SiGe block in the PFET region, and then forming Si fins and SiGe fins by patterning and reactive ion etching (RIE). Since Si and SiGe have different etch rates a practical problem arises using this approach. For example, Si fins and SiGe fins have different fin widths after fin patterning. Different fin widths cause a number of processing and structural issues that render the conventional techniques less than optimal.